1. Field of the Invention
The present invention relates generally to dynamic circuits and, more specifically, to dynamic logic circuits that include so-called weak feedback or keeper circuits for inhibiting noise-induced failures.
2. Description of the Related Art
Electronic logic circuits may be generally categorized into two types: static and dynamic. Static circuits include elements that, once set to one of the two binary logic states, will remain in that state essentially indefinitely, until the element is set to a different state or power to the circuit is removed. Dynamic circuits, in contrast, include elements that represent the binary logic state to which they are set by storing an electric charge in the manner of a capacitor. Because the charge typically dissipates within only a few milliseconds, a dynamic logic circuit must include a circuit for precharging it at intervals so that it maintains the logic state to which it was set until it is intentionally set to a different state. In accordance with the interval timing signals, which are generated by a suitable external clock circuit, in a typical dynamic logic circuit the charge is stored during a precharge phase and then conditionally discharged during an evaluation phase.
Defective components, charge leakage, electrical noise and other factors can cause logic circuits to fail, i.e, produce erroneous results. Dynamic logic is particularly susceptible to failure because any of a number of leakage and noise mechanisms can undesirably degrade or destroy the stored charge. As described below, so-called weak feedback circuits have been developed that inhibit noise-induced failures in dynamic logic, but they are not without disadvantages. The present invention addresses the disadvantages of prior dynamic logic circuits that include weak feedback and provides a solution.
For those readers who may not be skilled in the art to which the subject invention relates, a digital logic circuit operates in accordance with the theory of Boolean logic to enable computers and other digital electronic devices to perform mathematical computations, store data, control information flow and perform other functions. The basic units of digital logic are embodied in circuits known as gates. A gate that embodies the logical "and" function is known as an AND gate, and a gate that embodies the logical "or" function is known as an OR gate. A gate that inverts or produces the logical complement of the logic state of its input is known as a NOT gate or inverter. A gate that embodies the logical "exclusive-OR" function is known as an XOR gate. An AND gate that produces a complementary or inverted output is known as a NAND gate, and an OR gate that produces an inverted output is known as a NOR gate. A logic circuit may have one or more inputs, and a voltage can be applied to each input that represents one of the two binary logic states. The two states are referred to by the terms "high" and "low" or "1" and "0" or other contrasting terms. In response to these voltages, the logic circuit produces an output voltage that represents one of the two logic states. Whether a logic circuit interprets an input voltage as a high or low logic level depends on how much the voltage deviates from a nominal threshold level. If noise or other factors cause the voltage to deviate beyond predefined margins, the logic circuit may produce erroneous results. Extremely complex circuits, such as microprocessors, may be constructed on an integrated circuit chip that includes hundreds of thousands of these basic gates connected to one another. An erroneous output produced by even a single logic circuit may propagate through the network of interconnected logic circuits and result in total failure of the chip.
As illustrated in FIG. 1, a dynamic logic circuit 10 of the type known in the prior art as a domino circuit includes a precharge device such as a P-type field-effect transistor (PFET) 12. The gate terminal of PFET 12 is connected to the clock signal ("CLK"), the source terminal of PFET 12 is connected to the supply voltage signal (V.sub.DD), and the drain terminal of PFET 12 is connected to an input of a logic network 14. That input of logic network 14 is referred to as the dynamic node 16. Although not specifically illustrated in FIG. 1, logic network 14 typically comprises a network of one or more interconnected N-type field-effect transistors (NFETs) that may define any suitable gate type, such as AND or OR. Logic network 14 also receives one or more other input signals ("IN") that, depending upon the topology of its internal NFET network, define the conditions under which it discharges dynamic node 16. The output of logic network 14 is connected to the source terminal of an evaluate device such as a NFET 18. The gate terminal of NFET 18 is connected to the clock signal, and its drain terminal is connected to the ground signal (i.e., zero volts with respect to V.sub.DD). It is through NFET 18 that logic network 14 discharges dynamic node 16. A feedback or half-latch device such as another PFET 20 is connected in parallel with PFET 12, i.e., the source terminal of PFET 20 is connected to V.sub.DD and its drain is also connected to logic network 14. The input of an inverter 22 is connected to the dynamic node 16 of the circuit, i.e., the node at which the drain terminal of PFET 12 is connected to logic network 14. The output of inverter 22 provides the output signal ("OUT") of logic circuit 10. The output of inverter 22 is also connected to the gate terminal of PFET 20.
The leakage and noise mechanisms referred to above may include capacitive coupling to adjacent signals, charge sharing, subthreshold conduction through NFET logic transistors in logic network 14, and conduction through the NFET logic transistors due to noise on the inputs. If enough of the charge stored on dynamic node 16 is lost due to one or more of these mechanisms, the output of logic circuit 10 will transition to the incorrect state. This error can propagate to other gates (not shown) to which logic circuit 10 may be connected and cause a complete failure of a complex integrated circuit chip. To inhibit such charge loss on dynamic node 16, PFET 20 functions as a feedback device to feed back charge to dynamic node 16. The feedback is commonly referred to as "weak" because it is designed to be just barely sufficient to counter the expected charge loss due to the above-described effects.
Although the inclusion of a weak feedback circuit in logic circuit 10 addresses the charge loss problem, it adversely affects the performance of logic circuit 10. In the evaluation phase of operation, logic network 14 not only must discharge dynamic node 16 but also is forced to counter the charge supplied by PFET 16, increasing the time for dynamic node 16 to discharge. The discharge time is proportional to the size (i.e., current capacity) of the feedback device. It is not until the output of logic circuit 10 reaches a sufficiently high voltage level to turn off PFET 20 that PFET 20 stops providing charge, and this delay can adversely affect the operating speed any circuit that includes logic circuit 10.
To attempt to both minimize this delay and still inhibit charge loss, the designer of a dynamic circuit must consider the tradeoff between the potential impact on performance of providing substantial feedback by sizing the feedback device larger and the potential impact on reliability of not providing sufficient feedback by sizing the feedback device too small. Moreover, that variation in environmental conditions can be expected dictates that a designer design for the worst-case situation. For example, in reliability testing, circuits are subjected to higher voltages and temperatures than those under which they would normally be required to operate in order to stress the circuit and accelerate early failures. Typically, circuits undergoing reliability stress testing under such severe conditions are expected to operate at a much lower speed than at normal temperatures and voltage levels because such testing is intended to test logical functionality rather than speed. Thus, a circuit is considered to have passed the test so long as it exhibits the requisite logical functionality, regardless of whether it may operate at a lower speed under test than would be required or expected under normal operation.
Since higher temperatures and voltages can aggravate leakage and noise mechanisms, the designer typically includes a greater amount of feedback than is required for normal operation to ensure that the circuits remain functional under the most severe conditions. As discussed above, including a large amount of feedback in a dynamic circuit degrades performance, not only under stress conditions where high performance is not required, but also under normal conditions where high performance is paramount.
It would be desirable to provide a dynamic circuit that optimizes both functional operation and performance. These problems are satisfied by the present invention in the manner described below.